RISC-V 大杂烩

曾经的总目标: 从零开始用Verilog实现一个可以运行Linux的CPU

• Verilog
• 最简单,支持RV32I的CPU
• 添加流水线
• 添加特权模式
• MMU啥的

• 哪吒
• LicheeRV D1
• VisionFive

• RISC-V Assembly Programming
• Learn Risc-V Assembly Programming - Lesson1 : For absolute beginners!

• Verilog by Example: A Concise Introduction for FPGA Design
• ASIC-world Verilog page
• HDLBits—Verilog Practice

• RISC-V ASSEMBLY LANGUAGE Programmer Manual Part I 看起来不错的汇编教程
• RVCore Project, Arch Lab, Tokyo Tech
• RVSoC Project, a portable and Linux capable RISC-V computer system on an FPGA

• 自己动手写CPU: 从易到难实现了一个 MIPS CPU,感觉是本不错的书,但是MIPS 架构,不会优先考虑

  看了一半评价: 代码风格比较糟糕… 不过确实让我入门了一下Verilog = =

  • Single instruction cycle OpenMIPS: 通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构）， 简化成单指令周期实现的处理器
• CPU自制入门: 可能和上一本类似,但上一本优先考虑
• JuiceVm 可以在 ESP32 上跑的Linux虚拟机, 我震惊

OpenCores: The reference community for Free and Open Source gateware IP cores

在 Picorv32 / 蜂鸟 E203 软核上运行 RT-Thread: 用荔枝糖跑蜂鸟

Educational materials for RISC-V: archived

Chisel/FIRRTL Hardware Compiler Framework: 可以用来实现 RISC-V 核的语言

Learning FPGA, yosys, nextpnr, and RISC-V: 或许可以拿来学FPGA, 包括了多个1k行以内的RISC-V核,最小的只有400行

Dive Into Systems: 组原的开源教材

Lmxyy - Computer Architecture Task 2: Implement a Risc-v CPU using hardware description language(HDL), and then download the CPU on FPGA. Using C++ to simulate the memory via the USB-UART protocol.

Domipheus Labs — Designing a RISC-V CPU in VHDL

ICEBreaker上跑的双核RISC-V

F4PGA - open source FPGA toolchain

First Project: μLisp REPL over serial?

• DIY OPenMIPS: 比较可贵的事每篇都有实作心得 (虽然只到Ch9)

• UltraEmbedded 的三个核,从易到难
  • uriscv - Another tiny RISC-V implementation
  • RISC-V Core
  • biRISC-V - 32-bit dual issue RISC-V CPU
• List of RISC-V Cores: archived
• 果壳: 感觉doc不是很全面
• The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
  • cva6架构概述
  • OpenPiton: An Open Source Manycore Research Framework, 不知道是啥玩意
• VexRiscV — A FPGA friendly 32 bit RISC-V CPU implementation
• RISC-V BOOM — The Berkeley Out-of-Order RISC-V Processor: 是 out-of-order 的,感觉太高端了
• 香山 — 高性能开源RISC-V处理器: 太高端了
• DarkRISCV — opensouce RISC-V cpu core implemented in Verilog from scratch in one night!: 感觉不是很靠谱,不如蜂鸟
• RISCV-FiveStage: Chisel
• Simple RISC-V 3-stage Pipeline in Chisel
• FemtoRV
• tinyriscv 《从零开始写RISC-V处理器》 的配套代码

• chisel-bootcamp: chisel 教程
• 一些链接

• OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32: 从零开始用 Rust 语言写一个基于 RISC-V 架构的 类 Unix 内核
• Xv6 for RISC-V

• Ripes A graphical processor simulator and assembly editor for the RISC-V ISA